1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing that device. More particularly, the invention relates to a bipolar LSI and a BiCMOS (bipolar CMOS)-LSI having a structure for isolating elements by use of trenches.
2. Background Art
In recent years, the need for ever-faster processing prompted by improved driving capabilities of elements has led to widespread use of the BiCMOS-LSI wherein CMOS and bipolar transistors are formed on the same substrate.
FIG. 15 is a schematic cross-sectional view of a typical BiCMOS-LSI whose elements are isolated by trenches and whose passive elements include poly-poly capacitors and polysilicon resistances.
The BiCMOS-LSI shown in FIG. 15 has a P-type silicon semiconductor substrate 100 comprising an N-type buried layer 101a that is penetrated by trenches 104 filled with a polycrystalline silicon film 107a each, the trenches 104 serving for element isolation. On the N-type buried layer 101a is formed a P-type tab region 110 where NMOS transistors are formed. Also on the N-type buried layer 101a is formed an N-type epitaxial layer 102 where NPN bipolar transistors are fabricated. Certain areas of an element isolating oxide film 108 include a poly-poly capacitor (lower electrode 112b, upper electrode 121a, capacity coupling film 120a) and a polysilicon resistance 124b as passive elements.
A region where the NPN bipolar transistors are formed (called the NPN region hereunder) comes adjacent to a passive element region where the poly-poly capacitor (lower electrode 112b, upper electrode 121a, capacity coupling film 120a) and the polysilicon resistance 124b are formed, with a trench 104 interposed between the two regions. Another region where the NMOS transistors are formed (called the NMOS region hereunder) is located adjacent to the NPN region, also with a trench 104 interposed therebetween.
As illustrated in FIG. 15, the BiCMOS-LSI and bipolar LSI have conventionally adopted the element isolation structure utilizing the trenches 104 for isolation purposes. Only the trenches 104 in element-furnished portions isolate one element from another and separate each element from regions where no element is formed.
In the BiCMOS-LSI and bipolar LSI outlined above, the N-type buried layer 101a is not formed in the passive element region comprising the poly-poly capacitor (lower electrode 112b, upper electrode 121a, capacity coupling film 120a) and the polysilicon resistance 124b. The absence of the buried layer 101a is intended to reduce any parasitic capacity that may occur in the substrate. In addition, the passive element region tends to be formed in areas including the P-type tab region 110. As a result, the passive element region has the same potential as the substrate and develops a difference in potential from NPN regions nearby. With the BiCMOS-LSI in particular, a potential difference occurs between the MOS region where MOS transistors are formed on the one hand, and the NPN region where bipolar transistors are furnished on the other hand. In many cases, a backgate contact region of each N-channel MOS transistor in the BiCMOS-LSI is located close to other active elements across trenches 104.
If a potential difference occurs between the passive element region and the NPN region isolated by the trench 104, or between the NPN region and the MOS region, then conductive films such as the polycrystalline silicon film 107a filling the trenches 104 will develop a potential due to capacity coupling. That in turn leads to leaks (indicated by arrows in FIG. 15) channeled through the bottoms of the trenches 104, reducing a collector-to-substrate dielectric strength in the NPN transistors.
Furthermore, the trench-isolated structure in the bipolar LSI or BiCMOS-LSI is also subject to leaks if there is a potential difference between a no-element region in a chip edge portion and an element-furnished region. FIGS. 14A and 14B are schematic cross-sectional views of chip edge portions in the BiCMOS-LSI of FIG. 15. FIGS. 14A and 14B sketch chip edge portions fabricated by different methods.
As illustrated, the no-element region in the chip edge portion and the element-furnished region are located close to each other. If any no-element region develops a potential for some reason, there occurs a potential difference between the non-element region and the adjacent element-furnished region, which results in leaks.